Coating/developing units, using photolithography processes for manufacturing semiconductor devices and liquid crystal displays (LCD's), generally coat a resist on a substrate, expose the resist coating to light to impart a latent image pattern, and develop the exposed resist coating to transform the latent image pattern into a final image pattern having masked and unmasked areas. This permits deposition or treatment of selected portions of the surface of the semiconductor wafer. Such a series of processing stages is typically carried out in a coating/developing system having discrete heating sections, such as a post apply baking unit and a post exposure baking unit. Each heating section of the coating/developing system incorporates a hotplate with a built-in heater.
Feature sizes of semiconductor device circuits have been scaled to less than 0.1 microns. Typically, the pattern wiring that interconnects individual device circuits is formed with sub-micron line widths. Consequently, the heat treatment temperature of the resist coating should be accurately controlled to provide reproducible and accurate feature sizes and line widths. The substrates or wafers (i.e., objects to be treated) are usually treated or processed under the same process (i.e., individual treatment program) in units (i.e., lots) each consisting of, for example, twenty-five wafers. Individual processes define heat treatment conditions under which baking is performed. Wafers belonging to the same lot are heated under the same conditions.
The post exposure bake (PEB) process serves multiple purposes in photoresist processing. First, the elevated temperature of the bake drives the diffusion of the photoproducts in the resist. A small amount of diffusion may be useful in minimizing the effects of standing waves, which are the periodic variations in exposure dose throughout the depth of the resist coating that result from interference of incident and reflected radiation. Another main purpose of the PEB may be to drive an acid-catalyzed reaction that alters the solubility of the polymer layer used in many chemically amplified resists. PEB may also play a role in removing solvent from the wafer surface.
Hotplates having uniformities within a range of a few tenths of a degree centigrade are currently available and are generally adequate for current process methods. Hotplates are calibrated using a flat bare silicon wafer with imbedded thermal sensors. However, actual production wafers carrying deposited films on the surface of the silicon may exhibit small amounts of warpage because of the stresses induced by the deposited films. This warpage may cause the normal gap between the wafer and the hotplate (referred to as the proximity gap), to vary across the wafer from a normal value of approximately 100 μm by as much as a 100 μm deviation from the mean proximity gap (normal value).
This variability in the proximity gap changes the heat transfer into the wafer causing temperature variations on the wafer surface. These temperature differences in a PEB may result in a change in critical dimension (CD) in that area of several nanometers, which can approach the entire CD variation budget for current leading edge devices, and will exceed the projected CD budget for smaller devices planned for production in the next few years.
What is needed, therefore, is a method for heating a substrate during the pre- and post-exposure bake processes in a thermal processing system that is tolerant of warpage.